Academic Publications

Books

• Sid Touati and Benoît Dupont-de-Dinechin. Advanced Backend Code Optimization. ISTE, Wiley, 2014. ISBN-13: 978-1848215382.
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Refereed international journals

• Julien Worms and Sid Touati. Modelling Program’s Performance with Gaussian Mixtures for Parametric Statistics. In IEEE Transactions on Multi-Scale Computing Systems, September 2017. Issue 99.
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• Sid Touati, Sébastien Briais, Karine Deschinkel. How to eliminate non-positive circuits in periodic scheduling: a procative strategy based on shortest path equations. 20 pages. RAIRO-Operations Research, Volume 47. Issue 03. July 2013.
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• Sid Touati, Julien Worms, Sébastien Briais. The Speedup-Test: A Statistical Methodology for Program Speedup Analysis and Computation. 22 pages. Journal of Concurrency and Computation: Practice and Experience. Volume 25. Issue 10, pages 1410-1426. July 2013. Wiley edition.
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• Mounira Bachir, Sid Touati, Frederic Brault, David Gregg, Albert Cohen. Minimal Unroll Factor for Code Generation of Software Pipelining. International Journal of Parallel Programming. Volume 41, Issue 1 (2013), Pages 1-58. Springer. 2013.
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• Sid Touati and Frederic Brault and Karine Deschinkel and Benoît Dupont-de-Dinechin. Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types. ACM Transactions on Embedded Computing Systems. Volume 10, issue 4, November 2011. 25 pages.
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• Johnny Huynh and José Nelson Amaral and Paul Berube and Sid Touati. Evaluation of Offset Assignment Heuristics. ACM Transactions on Embedded Computing Systems. In Vol.10, No 3. 24 pages, April 2011.
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• Karine Deschinkel and Sid Touati and Sébastien Briais. SIRALINA: Efficient two-steps heuristic for storage optimisation in single period task scheduling. Journal of Combinatorial Optimization, Volume 22, Issue 4, Page 819-844, Springer, 2011.
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• Sid Touati and Zsolt Mathe. Periodic Register Saturation in Innermost Loops. Parallel Computing, volume 35, issue 4. 2009. pp. 239-254 (16 pages). Elsevier.
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• Sid Touati. On the Periodic Register Need in Software Pipelining. IEEE Transactions on Computers, Vol 56, issue 11, 16 pages, November 2007.
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• Sid Touati. Register Saturation in Instruction Level Parallelism. International Journal of Parallel Programming, Springer-Verlag, Volume 33, Issue 4, August 2005. 57 pages.
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• William Jalby, Christophe Lemuet and Sid Touati. An Efficient Memory Operations Optimization Technique for Vector Loops on Itanium 2 Processors. Concurrency and Computation: Practice and Experience. Volume 11, issue 11, september 2006, 26 pages, Wiley InterScience.
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• Sid Touati and Christine Eisenbeis. Early Periodic Register Allocation on ILP Processors. Parallel Processing Letters, Vol. 14, No. 2, June 2004. 27 pages. World Scientific.
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Refereed international conferences

• Carsten Bruns and Sid Touati. Understanding micro-architectural effects on the performance of parallel applications. In the proceedings of the International Conference on High Performance Computing and Simulation (HPCS 2020, online conference hold in March 2021).
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• Julien Worms and Sid Touati. Going beyond mean and median programs performances. IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2016). September 2016. Lyon, France.
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• Abdelhafid Mazouz, Sid Touati, Denis Barthou. Dynamic Thread Pinning for Phase-Based OpenMP Programs. Euro-Par 2013 Parallel Processing , Aachen, Germany. Springer, Lecture Notes in Computer Science Volume 8097, 2013, pp 53-64.
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• Mounira Bachir, Albert Cohen and Sid Touati. On the Effectiveness of Register Moves to Minimise Post-Pass Unrolling in Software Pipelined Loops. In the proceedings of the International Conference on High Performance ComputingSimulation (HPCS 2012), July 2012, Madrid. IEEE.
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• Mounira Bachir, Frederic Brault, Sid Touati and Albert Cohen. Loop Unrolling Minimisation in the Presence of Multiple Register Types: a Viable Alternative to Modulo Variable Expansion. In the 2011 International Conference on High Performance ComputingSimulation (HPCS 2011), July 2011, Istanbul. IEEE.
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• Abdelhafid Mazouz, Sid Touati and Denis Barthou. Performance Evaluation and Analysis of Thread Pinning Strategies on Multi-Core Platforms: Case Study of SPEC OMP Applications on Intel Architectures. In the 2011 International Conference on High Performance ComputingSimulation (HPCS 2011), July 2011, Istanbul. IEEE.
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• Samir Ammenouche, Sid Touati, William Jalby. On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors. In the proceedings of the 11th IEEE International Conference on High Performance Computing and Communications (HPCC-09). Korea University, Seoul, Korea. June 2009.
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• Karine Deschinkel and Sid Touati. Efficient Method for Periodic Task Scheduling with Storage Requirement Minimization. Proceedings of 2nd Annual International Conference on Combinatorial Optimization and Applications (COCOA 2008). Saint Johns, Newfoundland, Canada. August 2008, LNCS Springer.
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• Mounira Bachir, Sid Touati and Albert Cohen. Post-pass Periodic Register Allocation To Minimise Loop Unrolling. In the ACM proceedings of the Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2008), Tucson, Arizona.
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• Samir Ammenouche, Sid Touati and William Jalby. Practical Precise Evaluation of Cache Effects on Low Level Embedded VLIW Computing. In the 2008 High Performance Computing and Simulation Conference (HPCS 2008). ECMS proceedings. June 2008, Nicosia, Cyprus. Best paper award.
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• Sid Touati. Periodic Task Scheduling under Storage Constraints. In the proceedings of the Multidisciplinary International Scheduling Conference: Theory and Applications (MISTA’07), Paris, August 28-31, 2007.
• Johnny Huynh, Jose Nelson Amaral, Paul Berube, and Sid Touati. Evaluation of Offset Assignment Heuristics. International Conference on High Performance Embedded Architectures and Compilers (HiPEAC2007). Ghent, BELGIUM, January 28-30, 2007. LNCS, Springer.
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• Sid Touati and Denis Barthou. On the Decidability of Phase Ordering Problem in Optimizing Compilation. ACM Proceedings of the International Conference on Computing Frontiers. Ischia, Italy May 2-5, 2006.
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  Slides
• Christophe Lemuet and William Jalby and Sid Touati. Improving Load/Store Queues Usage in Scientific Computing. The International Conference on Parallel Processing (ICPP’04). Montreal, august 2004, IEEE.
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• Sid Touati and Christine Eisenbeis. Early Control of Register Pressure for Software Pipelined Loops. Springer-Verlag Lecture Notes in Computer Science, 2003. International Conference on Compiler Construction (CC), Warsaw, Poland, april, 2003.
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• Sid Touati. Optimal Acyclic Fine-Grain Schedule with Cache Effects for Embedded and Real Time Systems. ACM Proceedings of the Ninth International Symposium on Hardware/Software Codesign. Copenhagen, Denmark, April 25-27, 2001, IEEE.
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• Sid Touati. Register Saturation in superscalar and VLIW codes. Springer-Verlag Lecture Notes in Computer Science, 2001. International Conference on Compiler Construction, april, 2-6th 2001. Genova-Italy.
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• Abella, J., S. A. A. Touati, A. Anderson, C. Ciuraneta, J. M. Codina, Min Dai, C. Eisenbeis, G. Fursin, A. Gonzalez, J. Llosa, M. O’Boyle, A. Randrianatoavina, J. Sanchez, O. Temam, X. Vera, G. Watts. MHAOTEU Tools for Memory Hierarchy Management. IMACS’2000, Lausanne, Suisse, August 2000.
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Some mix of other refereed publications

• Mounira Bachir, Sid Touati and Albert Cohen. Decomposing Meeting Graph Circuits to Minimise Kernel Loop Unrolling. In the workshop on Optimizations for DSP and Embedded Systems (ODES’11), held in conjucntion with International Symposium on Code Generation and Optimization (CGO) Chamonix, France, 2011.
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• Abdelhafid Mazouz and Sid Touati and Denis Barthou. Analysing the Variability of OpenMP Programs Performances on Multicore Architectures. In the proceedings of the fourth workshop on programmability issues for heterogeneous multicores (MULTIPROG-2011), in conjunction with the HIPEAC conference. Heraklion, Greece. January 23, 2011.
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• Frédéric Brault and Benoît Dupont-de-Dinechin and Sid Touati and Albert Cohen. Software Pipelining and Register Pressure in VLIW Architectures: Preconditionning Data Dependence Graphs is Experimentally Better Than Lifetime-Sensitive Scheduling. Workshop on Optimizations for DSP and Embedded Systems (ODES’10). In conjunction with IEEE/ACM International Symposium on Code Generation and Optimization (CGO) Toronto, Canada, 2010.
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• Marouane Belaoucha and Denis Barthou and Adrien Eliche and Sid Touati. FADAlib: an Open Source C++ Library for Fuzzy Array Dataflow Analysis. In the proceedings of the Seventh International Workshop on Practical Aspects of High-level Parallel Programming (PAPP 2010). May 31- June 2, 2010, University of Amsterdam, The Netherlands. Elsevier.
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• Abdelhafid Mazouz and Sid Touati and Denis Barthou. Study of Variations of Native Program Execution Times on Multi-Core Architectures. IEEE International Workshop on Multi-Core Computing Systems (MuCoCoS 2010). Krakow, Poland, February 15, 2010.
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• Mounira Bachir and David Gregg and Sid Touati. Using The Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops. The 22nd International Workshop on Languages and Compilers for Parallel Computing (LCPC), Delaware, USA, October 2009.
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• Mohammed Fellahi, Albert Cohen, Sid Touati. Code-Size Conscious Pipelining of Imperfectly Nested Loops. MEDEA Workshop (MEmory performance DEaling with Applications, systems and architecture), held in conjunction with PACT 2007 Conference. Sept. 15-19 2007 Brasov, Romania.
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• Sid Touati. On the Optimality of Register Saturation. Electronic Notes in Theoretical Computer Science, Volume 132, Issue 1, 2005, Elsevier.
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• Sid Touati. EquiMax. A New Formulation of Acyclic Scheduling Problem for ILP Processors. Book chapter in Interaction between Compilers and Computer Architectures. Editors : Gyungho and Pen-Chung Yew. ISBN 0-7923-7370-7. Kluwer Academic Publishers, 2001.
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• Sid Touati. Maximizing for Reducing Register Need in Acyclic Schedules. 5th International Workshop on Software and Compilers for Embedded Systems, SCOPES ’2001. March 20th 2001. St Goar, Germany.
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• Min Dai, Christine Eisenbeis and Sid Touati. Load-Store Optimization for Software Pipelining. ACM SIGARCH Computer Architecture News, Volume 28, Number 1, march 2000.
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International workshops with invitations

• Samir Ammenouche, Sid Touati, William Jalby. Performance Study of Non-Blocking Caches for Embedded VLIW Processors. 14th Workshop on Compilers for Parallel Computing, CPC 2009, organised at IBM Zurich, Switzerland.
• Sid Touati. Minimizing Register Requirement in Loops Data Dependence Graphs. 10 th Workshop on Compilers for Parallel Computers, CPC 2003. January 2003, Amsterdam, NL.
  
• William Jalby, Christophe Lemuet and Sid Touati. Efficient Code Optimization Technique for Itanium2 Cache System and Scientific Computing. 10 th Workshop on Compilers for Parallel Computers, CPC 2003. January 2003, Amsterdam, NL.
  
• Sid Touati and Christine Eisenbeis. SIRA : Schedule Independent Register Allocation for Software Pipelining. 9th Workshop on Compilers for Parallel Computers, CPC 2001. June 27 - 29 Edinburgh, Scotland UK.
  

Research and technical reports

• Carsten Bruns and Sid Touati. Empirical study of Amdahl’s law on multicore processors. INRIA Research report number 9311. Université Côte d’Azur, France. Decembrer 2019.
  Link to HAL
• Julien Worms and Sid Touati. Parametric and Non-Parametric Statistics for Program Performance Analysis and Comparison. INRIA Research report number 8875. Université Nice Sophia Antipolis, Université Versailles Saint-Quentin en Yvelines. 70 pages and source code. March 2016.
  Link to HAL
• Abdelhafid Mazouz and Sid Touati and Denis Barthou. Measuring and Analysing the Variations of Program Execution Times on Multicore Platforms: Case Study. Research report, University of Versailles St-Quentin en Yvelines, number HAL-INRIA-00514548. July 2010.
  Link to HAL
• Sébastien Briais and Sid Touati and Karine Deschinkel. Ensuring Lexicographic-Positive Data Dependence Graphs in the SIRA Framework. Research report number HAL-INRIA-00452695. March 2010.
  Link to HAL
• Sid Touati and Julien Worms and Sébastien Briais. The Speedup-Test, declaring fair speedups with rigorous statistics. Technical Report number HAL-INRIA-00443839. January 2010.
  Link to HAL
• Sid Touati. Cyclic Task Scheduling with Storage Requirement Minimisation under Specific Architectural Constraints: Case of Buffers and Rotating Storage Facilities. Research report number HAL-INRIA-00440446. December 2009. University of Versailles Saint-Quentin en Yvelines.
  Link to HAL.
• Sébastien Briais and Sid Touati. Schedule-Sensitive Register Pressure Reduction in Innermost Loops, Basic Blocks and Super-Blocks. Research report number INRIA-HAL- 00436348. November 2009. University of Versailles Saint-Quentin en Yvelines.
  Link to HAL.
• Sébastien Briais and Sid Touati. Experimental Study of Register Saturation in Basic Blocks and Super-Blocks: Optimality and heuristics. Research report number INRIA-HAL-00431103. October 2009. University of Versailles Saint-Quentin en Yvelines.
  Link to HAL.
• Sid Touati and Christine Eisenbeis. Cyclic Register Pressure and Allocation for Modulo Scheduled Loops. INRIA Research Report, RR-4442, April 2002.
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• Sid Touati. Optimal Register Saturation in Superscalar and VLIW Codes. INRIA Research Report, RR-4263. September 2001.
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• Sid Touati and François Thomasset. Register Saturation in Data Dependence Graphs. INRIA Research Report, RR-3978. July 2000.
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• J. Abella, N. Bermudo, C. Ciuraneta, J. M. Codina, C. Eidenbeis, A. Gonzalez, J. Llosa, A. Randrianatoavina, F. Thomasset, S. A. A. Touati, X. Vera. Extended Performance Analysis. Deliverable M2.D1 of the MHAOTEU ESPRIT project no 24942, d cembre 1999.
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• J. Abella, M. Bull, C. Ciuraneta, J. M. Codina, C. Eisenbeis, P. Guillen, A. Gonzalez, J. Llosa, M. O. Boyle, A. Randrianatoavina, O. Temam, F. Thomasset, S. A. A. Touati, X. Vera, G. Watts. Process for Optimizing an Application. Deliverable M3D3 of the MHAOTEU ESPRIT project no 24942, 2000.
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• J. Abella, J. M. Codina, C. Ciuraneta, M. Dai, C. Eisenbeis, A. Gonzalez, J. Llosa, P. Knijnenburg, M. O’Boyle, S. A. A. Touati, X. Vera. Data Prefetching and Targeted Loop Optimizations. Deliverable M2.D2 of the MHAOTEU ESPRIT project no 24942, november 1999.
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• Jaume Abella, Grigori Fursin, Antonio Gonzalez, Josep Llosa, Mike O’Boyle, Abhishek Prabhat, Olivier Temam, Sid Touati, Xavier Vera, Gregory Watts. Advanced Performance Analysis. Deliverable M3.D1 of the MHAOTEU ESPRIT project no 24942, february 2001.
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• Philippe d’Anfray, Christine Eisenbeis, Eric Garnier, Philippe Guillen, Michael O’Boyle, Olivier Temam, Sid-Ahmed Ali-Touati, Gregory Watts. Interaction with Programers. Deliverable M3.D3 of the MHAOTEU ESPRIT project no 24942, february 2001.
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Tutorials in international conferences

I presented the Speedup-Test statistical protocol and tool in multiple half day tutorials in the following international conferences: HIPEAC 2010 (Pisa, Italy), CGO 2010 (Toronto, Canada), ICS 2010 (Tsukuba, Japan), HPCS 2010 (Caen, France), SAME 2012 (Sophia Antipolis, France). Link to the material (Full technical document, slides, and open source software).

Misc

• Sébastien Briais and Karine Deschinkel and Sid Touati. Elimination des circuits nuls dans les graphes cycliques pour l’ordonnancement périodique de tâches. Communication in ROADEF 2010, Toulouse (France),
• Karine Deschinkel et Sid Touati. Une heuristique efficace pour l’ordonnancement périodique de tâches avec contraintes de stockage. Communication in ROADEF 2009, Nancy (France),
• Sid Touati. Ordonnancement optimal et périodique de tâches sous contraintes d’espace de stockage. Communication in ROADEF 2007, Grenoble (France).
• Sid Touati. Impact des latences des loads sur l’allocation de registres dans les boucles vectorielles. Rapport interne, action EPICEA, université de Versailles St-Quentin en Yvelines. Juillet 2001.
• Sid Touati. Évaluation expérimentale de la vectorisation des opérations m émoire sur le besoin en registres. Rapport interne, action EPICEA, université de Versailles St-Quentin en Yvelines. Juin 2001.
• Sid Touati. Étude expérimentale sur le besoin en registres dans les boucles vectorielles. Rapport interne, action EPICEA, université de Versailles St-Quentin en Yvelines. Mars 2001.
• Sid Touati. Une méthode optimale et polynômiale d’optimisation de registres pour les expressions arithmétiques vectorielles ordonnancées par pipeline logiciel. Juin 2003. Rapport interne, action EPICEA, université de Versailles St-Quentin en Yvelines.
• Sid Touati. Étude des Performances de Codes sur les Processeurs à Parallélisme d’Instructions : Synthèse sur la Recherche et les Outils. Rapport d’étude. Novembre, 1999. université de Versailles St-Quentin en Yvelines.
  

Thesis

• Sid Touati. Backend Code Optimisation. Habilitation thesis. University of Versailles Saint-Quentin en Yvelines, June 30th, 2010.
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• Sid Touati. Register Pressure in Instruction Level Parallelism. PhD thesis. University of Versailles Saint-Quentin en Yvelines, INRIA. June 22th, 2002.
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Ce document a été traduit de L^AT_EX par H^EV^EA