News
23/05/2012 My PhD thesis has been published by "les éditions universitaires européennes". It is available as a hard cover book in french.
03/05/2012 A new STABLE release of K-Passa is now available. Click here!
16/01/2012 A new release of K-Passa is now available. Click here! Some bugs have been corrected in the "export to lucy-n" function. The balanced scheduling algorithm have been improved to deal with graphs with many strongly connected components. Moreover, a call to the LP-solver has been replaced by a polynomial function and thus the performances are much better. Some more improvements (bug fixes) will come shortly. The sources will be available shortly.
23/12/2011 The latest version of K-Passa is now available. Click here!
19/12/2011 I have completed to fill up my website's sections. I still have to translate the section "Research activities" in English.
16/12/2011:
The news is this website itself!
I'm still completing it using the latest web technologies: NotePad++, pure html, and CSS.
top
CV
[In pdf: En Français In English]PhD in Computer Science/ PostDoc in EPI AOSTE, INRIA Sophia-Antipolis
29 years old – INRIA Sophia-Antipolis, France– (+33)0603563330 – jvmillo[at]gmail[dot]comWork experiences
| 2011-2012 | Teaching assistant (90 hours) | University of Nice Sophia-Antipolis, France |
| 2011-2012 | PostDoc (1 year) | EPI Aoste, INRIA Sophia-Antipolis, France |
| 2009-2011 | PostDoc (2 years, 5 mois) | India Science Lab, General Motors R&D, Bangalore, India |
| 2006-2008 | PhD Student (3 years) | EPI Aoste, INRIA Sophia-Antipolis, France |
| 2005 | Research Engineer (10 months) | EPI Aoste, INRIA Sophia-Antipolis, France |
Diplomas
| 2008 |
PhD degree on embedded systems and SoC design « Ordonnancements périodique dans les réseaux de processus: application à la conception insensible aux latences ». Jury: Michel Auguin, Gaël Clavé, Marc Pouzet, Bruno Gaujal, et Robert de Simone |
University of Nice Sophia-Antipolis, France |
| 2005 | Engineering degree on embedded systems and telecom | ESIGETEL, Avon (77), France |
| 2005 | MSc degree on theoretical & applied computer science | University of Marne la Vallée, France |
| 2003 | BSc on computer science | University of Marne la Vallée, France |
| 2002 | French academic DUT on computer science | University of Nice Sophia-Antipolis, France |
| 2000 | French Baccalaureate in science (high school diploma) | Lycée Horticole d'Antibes, France |
skills
| Standards and Languages: Java, C, Latex, UML Marte, AUTOSAR, Petri Net, Esterel, SCADE, Lustre, Simulink/ Stateflow. |
| Research topics: Parallel computing, compiler and code optimization, SoC design, scheduling, verification and validation of hardware/ software design, synchronous languages, software product line, variability management, traceability management. |
| Theoretical Sciences: Concurrency theory (Petri net, Kahn network, synchronous data flow…), operational research, automata theory, combinatorial algebra. |
| Languages: English: Fluent, French: Mother tong |
| Sports: Volley-ball, Basket-ball (Coaching and playing) |
top
Publications
[In pdf (2nd page)]Under review (Journal: 4/ Conference: 2)
| Journal: | ||
| [GDMMBG2012] Minor revision required from editor | ||
| Calin Glitia, Julien DeAntoni, Frédéric Mallet, Pierre Boulet, Abdoulaye Gamatié, Jean-Vivien Millo | ||
| Scheduling and Deployment of Multidimensional Data Flow Applications with Marte | ||
| Special issue of Design Automation for Embedded System, Springer | ||
| [MdS2012] Minor revision required from editor | Bibtex | |
| Jean-Vivien Millo, Robert de Simone | ||
| Periodic scheduling of marked graphs using balanced binary words | ||
| Theoretical Computer Science, Elsevier | ||
| [MCR2011] | ||
| Anthony Coadou, Jean-Vivien Millo, S Ramesh | ||
| SDv: Scenario-Based Specification and Verification of SPL | ||
| CSI Journal of Computing | ||
| [MR2011] | ||
| Jean-Vivien Millo, S Ramesh | ||
| Toward Design Verification of Software Product Lines | ||
| ACM Transactions on Software Engineering and Methodology | ||
| Conference: | ||
| [MSR2011] | ||
| Swarup Mohalik, Jean-Vivien Millo, S Ramesh, Krishna S, Ganesh K | ||
| Formalizing Traceability and Derivability in Software Product Lines | ||
| SPLC’2012, Salvador, Brazil | ||
| [MS2012] | ||
| Jean-Vivien Millo, Robert de Simone | ||
| Towards globally configured NoC routing: Mapping an all-toall propagation algorithm onto a 2D-Torus NoC | ||
| EMSOFT'2012, Tampere, Finland |
Published (Journal: 2/ Conference: 3/ Workshop: 1/ Thesis: 1)
| Journal: | ||
| [BMS2007] | Bibtex | |
| Julien Boucaron, Jean-Vivien Millo, Robert de Simone | ||
| Formal methods of scheduling of Latency-insensitive designs | ||
| EURASIP journal on embedded system, 2007 | ||
| [BMS2006a] | Bibtex | |
| Julien Boucaron, Jean-Vivien Millo, Robert de Simone | ||
| Another glance at relay Stations in Latency-insensitive design | ||
| Electr. Notes Theor. Comput. Sci. Vol 146(no 2) pages 41-59, 2006 | ||
| Conference: | ||
| [MSR2011] | Bibtex | |
| Jean-Vivien Millo, Swarup Mohalik, S Ramesh | ||
| Integrated analysis of software product lines | ||
| ISEC’2011, Trivandrum, Kerala, India | ||
| [BMS2006b] | Bibtex | |
| Julien Boucaron, Jean-Vivien Millo, Robert de Simone | ||
| Latency-insensitive design: Dynamic and Static scheduling with proper formal devices | ||
| SAME'06, Sophia-Antipolis, France, 2006 | ||
| [BMS2006c] | Bibtex | |
| Julien Boucaron, Jean-Vivien Millo, Robert de Simone | ||
| Latency-insensitive design and central repetitive scheduling | ||
| MEMOCODE'06, pages 175-183, Piscataway, NJ, USA, 2006. IEEE Press | ||
| Workshop: | ||
| [BM2007] | Bibtex | |
| Julien Boucaron, Jean-Vivien Millo | ||
| Compositionality of Statically Scheduled IP | ||
| FMGALS Workshop, 2007 | ||
| Thesis: | ||
| [M2008] in French (at your own risk) | Bibtex | |
| Jean-Vivien Millo | ||
| Ordonnancements périodique dans les réseaux de processus: application à la conception insensible aux latences. | ||
| University of Nice Sophia-Antipolis, 2008 | ||
| My PhD thesis is available as an hard cover book | ||
| My PhD results have also been published in Periodic scheduling of marked graphs using balanced binary words |
top
Research activities
2005-2008: Modeling, Analysis, and optimization of embedded system with real-time constraint
My PhD thesis [M2008] was about static scheduling of Marked/Event Graph (MG). We have design an algorithm to statically schedule any MG with the best achievable throughput and the minimal token accumulation.
This work extends the theory of Latency Insensitive Design (LID). This last tackles the problem of latency on long interconnection wires in a System-on-Chip (SoC). A long latency breaks the synchronous hypothesis where communications are supposed to be instantaneous. In our first attempt [BMS2007], we tried to reduce the overhead of communication buffering required by the solution proposed by Luca Carloni in his thesis. To do so, we used the predictability of the MG. During my PhD, I have improved this method so that it always returns the optimal solution.
2009-2011: Formal Analysis of Software Product Line (SPL)
During my Post-Doc at India Science Lab, General Motors R\&D, Bangalore, India, I focus my interest on the representation of the variability in the SPL. Variability is the heart of an SPL but is not always considered as a first class citizen. It appears at every level of the software engineering flow (Requirement, Design, Implementation, and Test).
In a first work [MSR2010], we have extracted variability from every level of representation (feature diagram, architecture, behavioral model) and integrated it in a coherent framework across level. Thus we ran many analyzes based on consistency checking.
In a second work [MSR2011], we have focused our interest on the traceability across requirement and design still in the context of SPL.
In a third one [MR2011], we have proposed a design verification method that limits the combinatorial explosion of the complexity due to the presence of variability.
In the last one [MCR2011], we propose a scenario based language to write observer in the context of SPL. The full verification framework that checks the design against the observer is provided.
2011-*: Current interest
During my second Post-Doc, back to INRIA, I start to work on the modeling of highly parallel application. The goal is to ease the mapping of such an application on a parallel platform. Such mapping will be done ether at compile time or while refining our model in a language that explicit the structure of the targeted architecture including the computation elements but also the communication elements.
top
Teaching
I have started my teaching activities in 2011 at the university of Nice Sophia-Antipolis.Object oriented programmation and design pattern, Master 1 Miage, University of Nice Sophia-Antipolis
Languages and Automata, Licence 3 in computer science, University of Nice Sophia-Antipolis
HTML and CCS, DUT computer Science, University of Nice Sophia-Antipolis
Introduction to Database Management Systems, Licence 3 in computer science, University of Nice Sophia-Antipolis
Formal Models for Network-on-Chips (Foundations and models for the design of on-chip systems and networks), Master International Ubinet 2, Polytech Nice Sophia-Antipolis engineering school
top
Tools
K-PASSA v1.1
K-PASSA stands for "K-Periodic Asap Static Schedule Analyser". K-PASSA is for modeling and analysing Marked Graph. It implements the equalization process presented in Julien Boucaron's thesis but also the balanced scheduling algorithm presented in my thesis and in [MS2012].
A stand alone version of K-PASSA available >>>>>here<<<<<.
The current version is stable.
K-PASSA uses the lpsolve library as an LP solver.
To get it for 32/64 bit Unix/Linux and JDK 6, follow the link
Extract the two .so files from the archive and put them in /usr/lib.
Otherwise, put them where you want and set the LD_LIBRARY_PATH to this location.
To get it for 64 bit windows and JDK 6, follow the link
To get it for 64 bit Mac and JDK 6, follow the link
To get the same for other archi/OS, please go on the web site of lpsolve:
http://sourceforge.net/projects/lpsolve/.
Enjoy !
An open question:
The major upgrade from K-PASSA v1 to v1.1 is the balanced scheduling algorithm presented in [MS2012].
This algorithm is applicable to strongly connected graph however, K-PASSA allows simply connected graph.
To fill the gap, simply connected graphs are over constrained in strongly connected graphs in a brute force manner.
A smarter extension of the balanced scheduling algorithm to simply connected graph is still open.
Why K-PASSA v1.1 in parallel to
K-PASSA v2?
K-PASSA v1 has been developped in 2007. In 2008 and 2009, Julien Boucaron has developped
K-PASSA v2 from scratch. In K-PASSA v2, not only Marked Graph but also Latency Insensitive Design,
Synchronous Data Flow, and K-periodic Routing Graph can be manipulated and analysed.
After my Post-Doc in India Science Lab (GM R&D), I wanted to integrate in K-PASSA
the scheduling algorithm I developped during my PhD thesis. This algorithm is very
specific to Marked Graph and it has been easier for me to exdend the v1 that I have
built than discovering the internal structure of the v2.
top
