Jean-Vivien Millo

PhD in Computer Science
PostDoc in AOSTE team, I3S (CNRS/UNS)/ INRIA
Sophia-Antipolis, France
(+33)0603563330 – jean-vivien.millo [at] inria [dot] fr
jvmillo [at] gmail [dot] com







Current position

I'm currently in post-doc in the AOSTE team of INRIA Sophia-Antipolis. This team is common with the Univ. of Nice Sophia-Antipolis and CNRS (I3S laboratory). My current research projects are:

  • Generation of multi-threaded code from data-flow applications to MPPA platform.
  • Explicit routing of data-flow applications through a network on chip.
  • Verification of control design against scenarios using a synchronous approach.
  • Verification of the traceability between design and requirement in an SPL context.





Research interests

Modeling, Analysis, and optimization of embedded system with real-time constraint

My PhD thesis [M2008] was about static scheduling of Marked/Event Graph (MG). We have design an algorithm to statically schedule any MG with the best achievable throughput and the minimal token accumulation.

This work extends the theory of Latency Insensitive Design (LID). This last tackles the problem of latency on long interconnection wires in a System-on-Chip (SoC). A long latency breaks the synchronous hypothesis where communications are supposed to be instantaneous. In our first attempt [BMS2007], we tried to reduce the overhead of communication buffering required by the solution proposed by Luca Carloni in his thesis. To do so, we used the predictability of the MG. During my PhD, I have improved this method so that it always returns the optimal solution.

During my second Post-Doc, back to INRIA, I start to work on the modeling of highly parallel application. The goal is to ease the mapping of such an application on a parallel platform. Such mapping will be done ether at compile time or while refining our model in a language that explicit the structure of the targeted architecture including the computation elements but also the communication elements.

Formal Analysis of Software Product Line (SPL)

During my Post-Doc at India Science Lab, General Motors R\&D, Bangalore, India, I focus my interest on the representation of the variability in the SPL. Variability is the heart of an SPL but is not always considered as a first class citizen. It appears at every level of the software engineering flow (Requirement, Design, Implementation, and Test).

In a first work [MSR2010], we have extracted variability from every level of representation (feature diagram, architecture, behavioral model) and integrated it in a coherent framework across level. Thus we ran many analyzes based on consistency checking.

In a second work [MSR2012], we have focused our interest on the traceability across requirement and design still in the context of SPL.

In a third one [MRKG2013], we have proposed a design verification method that limits the combinatorial explosion of the complexity due to the presence of variability.

In the last one [MMCR2013], we propose a scenario based language to write observer in the context of SPL. The full verification framework that checks the design against the observer is provided.


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CV

[In pdf: English]


Work experiences


2013-2014 Assistant Professor on a fix term contract (ATER) University of Nice Sophia-Antipolis, France
2011-2013 PostDoc (2 years) and teaching assistant (200 hours) INRIA/ University of Nice Sophia-Antipolis, France
2009-2011 PostDoc (2 years and half) ISL, General Motors R&D, Bangalore, India
2006-2008 PhD Student (3 years) EPI Aoste, INRIA Sophia-Antipolis, France
2005 Research Engineer (10 months) EPI Aoste, INRIA Sophia-Antipolis, France

Diplomas


2008 PhD degree on embedded systems and SoC designUniversity of Nice Sophia-Antipolis, France
« Ordonnancements périodique dans les réseaux de processus:
application à la conception insensible aux latences ».
Jury: Michel Auguin, Gaël Clavé, Marc Pouzet,
Bruno Gaujal, et Robert de Simone
2005 Engineering degree on embedded systems and telecom ESIGETEL, Avon (77), France
2005 MSc degree on theoretical & applied computer science University of Marne la Vallée, France
2003 BSc on computer science University of Marne la Vallée, France
2002 French academic DUT on computer science University of Nice Sophia-Antipolis, France
2000 French Baccalaureate in science (high school diploma) Lycée Horticole d'Antibes, France

skills


Areas of expertise: High level modeling of embedded and real-time system, Algorithms, Design patterns, Multithreading, Compiler and code optimization, SoC design, Scheduling, Verification and validation of hardware/ software design, Concurrency theory, Models of computation and communication, Synchronous languages, Software product line, Variability management.
Standards and Languages: Java, C, Linux system (scripting, programming), C++, SVN (GIT), Simulink/Stateflow, Esterel, SCADE, Promela/SPIN, Yices, nuSMV, LaTeX, Hardware architecture, GPGPU, System C, UML Marte, AUTOSAR, Eclipse (EMF), CUDA, OpenCL, OpenMP, MPI, SQL (Oracle), HTML, networking.
Professional skills: Project management, team working, International collaboration, (small) team management, Technical presentation and communication (writing and oral), Training, reviewing external work.
Languages: English: Fluent, French: Mother tong
Sports: Climbing, Hiking, Volley-ball, Basket-ball (Coaching and playing)

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Publications

[pdf] [Bibtex]

PhD Thesis:

[M2008] in FrenchPDFBibtex
Jean-Vivien Millo
Ordonnancements périodique dans les réseaux de processus: application à la conception insensible aux latences.
University of Nice Sophia-Antipolis, December 2008
My PhD thesis is available as a soft cover book [French]
My PhD results have also been published in [MdS2012] in English

International peer reviewed journals:

[MS2013]PDFBibtex
Jean-Vivien Millo, Robert de Simone
Explicit routing schemes for implementation of cellular automata on processor arrays
Special issue of Natural Computing, Springer Netherlands, May 2013
[MdS2012]PDFBibtex
Jean-Vivien Millo, Robert de Simone
Periodic scheduling of marked graphs using balanced binary words
Theoretical Computer Science, Volume 458, pages 113-130, November 2012, Elsevier
[GDMMBG2012]PDFBibtex
Calin Glitia, Julien DeAntoni, Frédéric Mallet, Jean-Vivien Millo, Pierre Boulet, Abdoulaye Gamatié
Progressive and Explicit Refinement of Scheduling for Multidimensional Data-Flow Applications using UML MARTE
Special issue of Design Automation for Embedded System, Volume 16, Issue 2, pages 137-169, 2012, Springer Netherlands
[BMS2007]PDFBibtex
Julien Boucaron, Jean-Vivien Millo, Robert de Simone
Formal methods of scheduling of Latency-insensitive designs
EURASIP journal on Embedded System, Volume 2007, pages 8--8, January 2007

International peer reviewed conferences:

[MMb2013]PDFBibtexSlides
Frédéric Mallet,Jean-Vivien Millo, Robert de Simone
Safe CCSL specifications and marked graphs
11th International Conference on Formal Methods and Models for Codesign (MEMOCODE 2013), Portland, Oregon, USA, October 2013
[MMa2013]PDFBibtex
Frédéric Mallet,Jean-Vivien Millo
Boundness Issues in CCSL Specifications
15th International Conference on Formal Engineering Methods, Queenstown, New Zealand, October 2013
[GKM2013] PDFBibtex
Arda Goknil, Ivan Kurtev, Jean-Vivien Millo
A Metamodeling Approach for Reasoning on Multiple Requirements Models
IEEE International EDOC Conference, September 2013, Vancouver, Canada
[MRKG2013] PDFBibtex
Jean-Vivien Millo, S Ramesh, S Krishna, Ganesh N
Compositional Verification of Software Product Lines
Integrated Formal Methods 2013, Turku, Finland
[MSR2012]PDFBibtex
Swarup Mohalik, Jean-Vivien Millo, S Ramesh, Krishna S, Ganesh K
Tracing SPLs Precisely and Efficiently
SPLC’2012, Salvador, Brazil, September 2012
[MSR2011]PDFBibtex
Jean-Vivien Millo, Swarup Mohalik, S Ramesh
Integrated analysis of software product lines
ISEC’2011, Trivandrum, Kerala, India, February 2011
[BMS2006c]PDFBibtex
Julien Boucaron, Jean-Vivien Millo, Robert de Simone
Latency-insensitive design and central repetitive scheduling
MEMOCODE'06, pages 175-183, Piscataway, NJ, USA, July 2006

International invited journal:

[MMCR2013] PDFBibtex
Jean-Vivien Millo, Frédéric Mallet, Anthony Coadou, S Ramesh
Scenario-based verification in presence of variability using a synchronous approach
Invited paper in Frontiers of Computer Science, Springer

Workshops:

[MRsqam2012]PDFBibtexVideo
Jean-Vivien Millo, S Ramesh
Relating Requirement and Design Variabilities
SQAM’2012, Hong Kong, December 2012
[MS2012]PDFBibtex
Jean-Vivien Millo, Robert de Simone
Refining cellular automata with routing constraints
Automata and JAC 2012, Bastia, Corsica, France, September 2012
[BM2007]PDFBibtex
Julien Boucaron, Jean-Vivien Millo
Compositionality of Statically Scheduled IP
FMGALS Workshop, Nice, France, July 2007
[BMS2006a]PDFBibtex
Julien Boucaron, Jean-Vivien Millo, Robert de Simone
Another glance at relay Stations in Latency-insensitive design
Electr. Notes Theor. Comput. Sci. Volume 146, issue 2, pages 41-59, 2006

Miscellaneous:

[BMS2006b]PDFBibtex
Julien Boucaron, Jean-Vivien Millo, Robert de Simone
Latency-insensitive design: Dynamic and Static scheduling with proper formal devices
SAME'06, Sophia-Antipolis, France, October 2006

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Teaching

2013-14

Advanced Object oriented programing, First year, Master miage, University of Nice Sophia-Antipolis

Design Pattern, First year, Master miage, University of Nice Sophia-Antipolis

System and network, Third year, Licence Miage, University of Nice Sophia-Antipolis

Database, Third year, Licence Miage, University of Nice Sophia-Antipolis

Object oriented programing, Third year, Licence Miage, University of Nice Sophia-Antipolis

Concurrency and parallelism, First year, International master in computer science, University of Nice Sophia-Antipolis

Models for temporal and functionnal analyses, First year, master in computer science, University of Nice Sophia-Antipolis

System, First year, Licence in computer science, University of Nice Sophia-Antipolis

2012-13

Advanced Object oriented programing, First year, Master miage, University of Nice Sophia-Antipolis

Concurrency and parallelism, First year, International master in computer science, University of Nice Sophia-Antipolis

System, First year, Licence in computer science, University of Nice Sophia-Antipolis

2011-12

Object oriented programing and design pattern, First year, Master miage, University of Nice Sophia-Antipolis

Languages and Automata, Licence 3 in computer science, University of Nice Sophia-Antipolis

HTML and CCS, DUT computer Science, University of Nice Sophia-Antipolis

Introduction to Database Management Systems, Licence 3 in computer science, University of Nice Sophia-Antipolis

Formal Models for Network-on-Chips (Foundations and models for the design of on-chip systems and networks), Master International Ubinet 2, Polytech Nice Sophia-Antipolis engineering school


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Last update: 11/12/2013

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