SubClock:
This is a synchronous temporal relation that prevents one clock (the subclock) from ticking when another master clock (the superclock) does not tick.
Example of CCSL specification:
/*
* c1 is subclock of c2
* @author: Julien DeAntoni
* date : Wed jul 8th 2011
*/
ClockConstraintSystem MySpec {
imports {
import "ccsl:kernel" as kernelLib ; //add the kernel constraints to your specification
}
entryBlock main
Block main {
Clock c1
Clock c2
Relation r1[SubClock](LeftClock -> c1, RightClock -> c2 )
}
}
Simulation results:
The subClock relation is simulated in the next picture. Some ticks of c2 occurs at the same time than a tick of c1.
On the bottom right, the clock domain is represented; here, the two clocks are linked by a subclock relation.
