Concatenation:
Concatenation is surely the most complicated expression. However the principle is quite simple. As all expressions, it creates an implicit clock that is the result of the expression.
The expression takes two arguments. The implicit clock ticks in coincidence with the first argument 'LeftClock' (ie c1 in the example) until the 'LeftClock' dies. After the die of the 'LeftClock', the implicit clock ticks in coincidence with the 'RightClock''. Note that, if the 'RightClock' is not used elsewhere in the specification, its birth coincides with the dead of the 'LeftClock'. Finally, it can be complex to understand because, as explain at the end of this page, the concatenation can be recursive.
A simple example is given below where the 'LeftClock' is an expression that dies (ie a wait expression). The 'RightClock' birth coincides with the 'LeftClock' dead.
Once c2 ticked, the implicit clock is dead. Note that the death is propagated by the coincidence relation so that, in the example, c3 dies at the same time than the implicit clock.
the CCSL specification:
/*
* myConcat = (c1 wait 5) concatWith (c1 wait 6)
* @author: Julien DeAntoni
* date : Mon jul 25th 2011
*/
ClockConstraintSystem MySpec {
imports {
import "ccsl:kernel" as kernelLib ; //add the kernel constraints to your specification
}
entryBlock main
Block main {
Clock c1
Clock c2
Integer i=5
Integer j=6
Expression c1wait5 = Wait( WaitingClock -> c1, WaitingValue-> i )
Expression c1wait6 = Wait( WaitingClock -> c1, WaitingValue-> j )
Expression myConcat=Concatenation( LeftClock-> c1wait5, RightClock-> c1wait6 )
}
}
Simulation results:
The simulation of the previous example is represented on the next picture. The first ticks of the implicit clock coincidences with the 5th tick of c1 and the second one with the 11th tick of c1 (the 6th that follows the death of the 'LeftClock'). Moreover, as you can see, when the 'RightClock' dies, it simultaneously implies the death of the implicit clock.
On the bottom right, the clock domain is represented; here, the implicit clock is a sequence of two clocks. The sequence is a specific kind of subclocking.
It is important to notice that, without the concatenation in the previous specification, the result of c1wait6 would not be the same because its birth would be the beginning of the simulation. In this case the simulation would be:
TODO recursive concatenation
