Publications » 2010

Book Chapters

1. André, C., DeAntoni, J., Mallet, F., and Simone, R. de. 2010. The Time Model of Logical Clocks Available in the OMG MARTE Profile. In: S.K. Shukla and J.-P. Talpin, eds., Springer Science + Business Media, 201–227. ^DOI

   @incollection{Shukla2010,
     chapter = {7},
     pages = {201--227},
     title = {The Time Model of Logical Clocks Available in the OMG MARTE Profile},
     publisher = {Springer Science + Business Media},
     year = {2010},
     editor = {Shukla, Sandeep K and Talpin, {Jean-Pierre}},
     author = {Andr\'e, Charles and DeAntoni, Julien and Mallet, Fr\'ed\'eric and de Simone, Robert},
     series = {In Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction Software Design},
     month = jun,
     doi = {10.1007/978-1-4419-6400-7_7}
   }
   

2. Mallet, F., André, C., and Simone, R. de. 2010. IP-Xact components with Abstract Time Characterization. In: D. Borrione, ed., Advances in Design Methods from Modeling Languages for Embedded Systems and SoCs. Springer, 3–18. ^DOI

   @incollection{FdlSpringer2010,
     chapter = {1},
     pages = {3--18},
     title = {{IP-Xact} components with Abstract Time Characterization},
     author = {Mallet, Fr\'ed\'eric and Andr\'e, Charles and de Simone, Robert},
     publisher = {Springer},
     year = {2010},
     editor = {Borrione, Dominique},
     volume = {63},
     series = {LNEE},
     month = jul,
     booktitle = {Advances in Design Methods from Modeling Languages for Embedded Systems and SoCs},
     doi = {10.1007/978-90-481-9304-2_1}
   }
   

Journal Articles

1. Mallet, F., André, C., and Lagarde, F. 2010. Un processus automatique pour concevoir les profils UML. Technique et Sciences Informatiques 29, 4–5, 391–419.

   @article{TSI10,
     author = {Mallet, Fr\'ed\'eric and Andr\'e, Charles and Lagarde, Fran\c{c}ois},
     title = {Un processus automatique pour concevoir les profils {UML}},
     journal = {Technique et Sciences Informatiques},
     volume = {29},
     number = {4--5},
     year = {2010},
     month = {Mai},
     pages = {391--419}
   }
   

2. Mallet, F., DeAntoni, J., André, C., and de Simone, R. 2010. The clock constraint specification language for building timed causality models. Innovations in Systems and Software Engineering 6, 1–2, 99–106. ^DOI

   @article{ISSE10,
     author = {Mallet, Fr\'ed\'eric and DeAntoni, Julien and Andr\'e, Charles and {de Simone}, Robert},
     title = {The clock constraint specification language for building timed causality models},
     journal = {Innovations in Systems and Software Engineering},
     volume = {6},
     number = {1--2},
     year = {2010},
     pages = {99--106},
     doi = {10.1007/s11334-009-0109-0}
   }
   

Conference Articles

1. Mallet, F., Lagarde, F., André, C., Gérard, S., and Terrier, F. 2009. An Automated Process for Implementing Multilevel Domain Models. SLE, Springer, 314–333. ^DOI

   @inproceedings{MalletLAGT09,
     author = {Mallet, Fr{\'e}d{\'e}ric and Lagarde, Fran\c{c}ois and Andr{\'e}, Charles and G{\'e}rard, S{\'e}bastien and Terrier, Fran\c{c}ois},
     title = {An Automated Process for Implementing Multilevel Domain
                    Models},
     booktitle = {SLE},
     year = {2009},
     pages = {314--333},
     doi = {10.1007/978-3-642-12107-4_22},
     location = { Denver, CO, USA},
     publisher = {Springer},
     series = {Lecture Notes in Computer Science},
     volume = {5969},
     isbn = {978-3-642-12106-7}
   }
   

2. Glitia, C., DeAntoni, J., and Mallet, F. 2010. Logical Time at Work: Capturing Data Dependencies and Platform Constraints. FDL, ECSI, Electronic Chips & Systems design Initiative, 241–248. ^DOI

   @inproceedings{DBLP:conf/fdl/GlitiaDM10,
     author = {Glitia, Calin and DeAntoni, Julien and Mallet, Fr{\'e}d{\'e}ric},
     title = {Logical Time at Work: Capturing Data Dependencies and Platform
                    Constraints},
     booktitle = {FDL},
     year = {2010},
     pages = {241--248},
     doi = {10.1049/ic.2010.0159},
     location = { Southampton, UK},
     publisher = {ECSI, Electronic Chips {\&} Systems design Initiative}
   }
   

3. DeAntoni, J., Mallet, F., Thomas, F., et al. 2010. RT-simex: retro-analysis of execution traces. SIGSOFT FSE, ACM, 377–378. ^URL

   @inproceedings{DBLP:conf/sigsoft/DeAntoniMTRBMGRS10,
     author = {DeAntoni, Julien and Mallet, Fr{\'e}d{\'e}ric and Thomas, Fr{\'e}d{\'e}ric and Reydet, Gonzague and Babau, Jean-Philippe and Mraidha, Chokri and Gauthier, Ludovic and Rioux, Laurent and Sordon, Nicolas},
     title = {RT-simex: retro-analysis of execution traces},
     booktitle = {SIGSOFT FSE},
     year = {2010},
     pages = {377--378},
     url = {http://doi.acm.org/10.1145/1882291.1882357},
     publisher = {ACM},
     isbn = {978-1-60558-791-2}
   }
   

4. André, C., Mallet, F., and DeAntoni, J. 2010. VHDL Observers for Clock Constraint Checking. SIES, IEEE, 98–107. ^DOI

   @inproceedings{DBLP:conf/sies/AndreMD10,
     author = {Andr{\'e}, Charles and Mallet, Fr{\'e}d{\'e}ric and DeAntoni, Julien},
     title = {VHDL Observers for Clock Constraint Checking},
     booktitle = {SIES},
     year = {2010},
     pages = {98--107},
     doi = {10.1109/SIES.2010.5551372},
     publisher = {IEEE},
     isbn = {978-1-4244-5840-0}
   }