Dehui Du, Ping Huang, F. Mallet, Mingrui Yang and Kaiqiang Jiang.
MARTE/pCCSL: Modeling and Refining Stochastic Behaviors of CPSs with Probabilistic Logical Clocks.DOI(Best Paper Award) Formal Aspects of Component Software - 13th Int. Conf. (FACS'16), LNCS 10231, pp. 111-133, Springer, Oct. 2016.
Aamir M. Khan, F. Mallet and Muhammad Rashid.
Natural interpretation of UML/MARTE diagrams for system requirements
specification.DOI 11th IEEE Symp. on Industrial Embedded Systems (SIES'16), pp. 193-198, IEEE, May 2016.
Daian Yue, Vania Joloboff and F. Mallet.
Flexible runtime verification based on logical clock constraints.DOI 2016 Forum on Specification and Design Languages, FDL (FDL'16), pp. 1-8, IEEE, Sep. 2016.
Min Zhang, F. Mallet and Huibiao Zhu.
An SMT-Based Approach to the Formal Analysis of MARTE/CCSL.DOI Formal Methods and Software Engineering - 18th Int. Conf.
on Formal Engineering Methods (ICFEM'16), LNCS 10009, pp. 433-449, Springer, Nov. 2016.