Hardware Architecture Modelling using an Object-oriented Method
Frédéric MALLET*,
Fernand BOERI* Senior Member IEEE
and Jean-François DUBOC**
* Laboratoire I3S, UPRES_A 6070 CNRS, Université de Nice-Sophia Antipolis
** VLSI Technology inc., 505 Route des Lucioles, Sophia-Antipolis 06560 Valbonne.
Abstract:
The very high integration rate and the increasing complexity of digital hardware architectures
and embedded applications lead designers to search for new tools and methods. In order to reduce
the time-to-market it becomes essential to allow designers to evaluate performances of a given application with the targeted architecture very soon in the design phase. So we have decided to build a modelling simulation environment in order to evaluate the requisite number of cycles for processing a given application with a simple model of digital hardware architecture.
Then, our main objective and the greatest part of our work is to describe this environment with an example based on the Pine DSP and some classical digital signal processing applications: FIR, FFT butterfly, Viterbi's Butterfly.
© 1998 IEEE Computer Press.
@inproceedings{MBD:Euromicro1998,
author = {Fr{\'e}d{\'e}ric Mallet and
Fernand Bo{\'e}ri and
Jean-Fran\c{c}ois Duboc},
title = {Hardware Architecture Modelling Using an Object-Oriented
Method},
booktitle = {Euromicro Conference, 1998. Proceedings. 24th},
year = {1998},
volume = {1},
pages = {147--153},
address = {Vasteras},
month = aug,
ee = {http://csdl.computer.org/comp/proceedings/euromicro/1998/8646/01/864610147abs.htm},
crossref = {DBLP:conf/euromicro/1998},
doi = {10.1109/EURMIC.1998.711789},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
@proceedings{DBLP:conf/euromicro/1998,
title = {24th EUROMICRO '98 Conference, Engineering Systems and Software
for the Next Decade, 25-27 August 1998, Vesteras, Sweden},
booktitle = {EUROMICRO},
publisher = {IEEE Computer Society},
year = {1998},
isbn = {0-8186-8646-4},
bibsource = {DBLP, http://dblp.uni-trier.de}
}