Hardware modelling and simulation using an object-oriented method

Abstract: Digital hardware architectures and embedded applications are increasingly complex. The very high integration rate and the increasing complexity lead designers to search for new tools and methods. In order to reduce the cost, the time-to-market and to make the most pertinent choices, it becomes essential to allow designers to evaluate, very soon in the design phase, a given application performances with the targeted architecture. So we have decided to build a modelling and simulation environment in order to evaluate digital hardware architectures performances. We aim mainly at evaluating the requisite number of cycles for processing a given application with a simple model of the architecture.

In this project, we need to increase the reusability with an adjustable abstraction level. This is not a recent problem and object-oriented methods were born in order to solve this problem for software systems. For a few years, lots of international projects (RASSP from the American Department of Defence; POLIS from the University of Berkeley, California) have tried to find an object-oriented solution for hardware systems. One result of these projects consists in the definition of an object-oriented layout upon VHDL, which is with Verilog one of the two most used hardware description languages. But, VHDL is a very heavy language designed to synthesise hardware systems and it includes lots of mechanisms, which are useless in the first steps of the design phase. So, we have chosen to construct upon Java - an entire and pure object-oriented language - mechanisms, which will permit designers to model and simulate hardware architectures. Object orientation includes abstraction and encapsulation mechanisms and allows polymorphism and inheritance. Then, reusing already designed components, designers will be able to build models with a level of abstraction which fit theirs goals.
Then, our main objective and the greatest part of our work were to define a generic object-oriented model of digital hardware architectures. This paper mainly consists in the explanation of this model, which is designed to help us to implement a visual modelling and simulation environment. The designer should proceed in an incremental way, assembling already existing components from libraries and building new ones. At each step, the designer can choose the right abstraction level. The low reasonable description level appears to be the register level.
So, we have proceeded in several steps. The first step was to define the main characteristics of the targeted digital architectures. We would have liked to have a generic description with few constraints in order to be able to study not only simple processors but also multi-core or distributed architectures. The second step was to determine basic components of these targeted architectures in order to make a standard basic library of reusable components. These components (multiplexer, register, ALU, memory) were to constitute entities the description of which has the lowest abstraction level. The third step was to choose and apply an object-oriented design method in order to construct a generic object-oriented framework for the description and the simulation of the targeted architectures and applications. We have chosen OMT (Object Modelling Technique) because it is very used and it is simpler than UML (Unified Modelling Language). Moreover, it seems to be sufficient for our description. Here we are able to describe each of the targeted architectures from a basic specification like a simplified block diagram. Applying this technique, we had constructed a simple simulatable model of a real digital signal processor in a few weeks. This model uses a reduced subset of the real assembly language of the processor for modelling applications. The last step is going to be the construction of a visual interface, which can use the proposed object-oriented model. This is about to be done using the Java Development Kit 1.1.5 (or 1.2 if released) and the interface will be described in a following paper.