Publications » 2016

Conference Articles

  1. Du, D., Huang, P., Mallet, F., Yang, M., and Jiang, K. 0AD. MARTE/pCCSL: Modeling and Refining Stochastic Behaviors of CPSs with Probabilistic Logical Clocks. IC. on Formal Aspects of Component Software - FACS, Springer, 111–133. DOI (Best Paper Award)
    @inproceedings{Du2016,
      title = {{MARTE/pCCSL}: Modeling and Refining Stochastic Behaviors of {CPSs} with Probabilistic Logical Clocks},
      author = {Du, Dehui and Huang, Ping and Mallet, Fr{\'{e}}d{\'{e}}ric and Yang, Mingrui and Jiang, Kaiqiang},
      year = {2017},
      pages = {111--133},
      publisher = {Springer},
      month = oct,
      comment = {Best Paper Award},
      doi = {10.1007/978-3-319-57666-4},
      booktitle = {IC. on Formal Aspects of Component Software - FACS},
      editor = {Kouchnarenko, Olga and Khosravi, Ramtin},
      series = {Lecture Notes in Computer Science},
      volume = {10231},
      date = {October 19-21},
      isbn = {978-3-319-57665-7},
      location = {Besan{\c{c}}on, France}
    }
    
  2. Khan, A.M., Mallet, F., and Rashid, M. 2016. Natural interpretation of UML/MARTE diagrams for system requirements specification. 11th IEEE Symposium on Industrial Embedded Systems, IEEE, 193–198. URL DOI
    @inproceedings{KhanMR16,
      title = {Natural interpretation of {UML/MARTE} diagrams for system requirements
       specification},
      author = {Khan, Aamir M. and Mallet, Fr{\'{e}}d{\'{e}}ric and Rashid, Muhammad},
      booktitle = {11th {IEEE} Symposium on Industrial Embedded Systems},
      year = {2016},
      pages = {193--198},
      doi = {10.1109/SIES.2016.7509429},
      month = may,
      publisher = {IEEE},
      isbn = {978-1-5090-2282-3},
      location = {Krakow, Poland},
      url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7504669}
    }
    
  3. Yue, D., Joloboff, V., and Mallet, F. 0AD. Flexible runtime verification based on logical clock constraints. 2016 Forum on Specification and Design Languages, FDL, IEEE, 1–8. URL DOI
    @inproceedings{YueJM16,
      title = {Flexible runtime verification based on logical clock constraints},
      author = {Yue, Daian and Joloboff, Vania and Mallet, Fr{\'{e}}d{\'{e}}ric},
      year = {2016},
      pages = {1--8},
      month = sep,
      date = {September 14-16},
      doi = {10.1109/FDL.2016.7880366},
      location = {Bremen, Germany},
      booktitle = {2016 Forum on Specification and Design Languages, {FDL}},
      editor = {Drechsler, Rolf and Wille, Robert},
      publisher = {IEEE},
      isbn = {979-10-92279-17-7},
      url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7879501}
    }
    
  4. Zhang, M., Mallet, F., and Zhu, H. 2016. An SMT-Based Approach to the Formal Analysis of MARTE/CCSL. 18th IC. on Formal Engineering Methods - ICFEM, Springer, 433–449. DOI
    @inproceedings{ZhangMZ16,
      title = {An SMT-Based Approach to the Formal Analysis of {MARTE/CCSL}},
      author = {Zhang, Min and Mallet, Fr{\'{e}}d{\'{e}}ric and Zhu, Huibiao},
      year = {2016},
      publisher = {Springer},
      pages = {433--449},
      doi = {10.1007/978-3-319-47846-3_27},
      booktitle = {18th IC. on Formal Engineering Methods - ICFEM},
      editor = {Ogata, Kazuhiro and Lawford, Mark and Liu, Shaoying},
      month = nov,
      series = {Lecture Notes in Computer Science},
      volume = {10009},
      isbn = {978-3-319-47845-6},
      location = {Tokyo, Japan}
    }