Known Bugs and Fixes

This page gives all the currently known bugs and possibly gives access to corrections. Once a bug has been corrected, the Esterel distribution is updated. Thus, if you download the latest release of Esterel, you will have the corrected processors.

Nevertheless, if you already have the current distribution, you probably just want to download the corrected processor(s). The following table sums them up:

Processor	Patch level	Architectures
lcsc (Esterel Core)	v87-v5_22	sunsolaris sunos5_5 linux Windows NT IBM AIX Dec OSF1
occ (C code generator)	p54 with common(p41)	Sun Solaris 5.6
Wrong Simulation		Scripts
sscoc	no patch
Textual Simulator on Solaris
Causality analyzer	p78a	Linux RedHat 5.6 Windows NT 4.0 Sun Solaris 5.6 Dec Osf 1

The columns are:

Processor: gives the name of the processor to download. It is an hyperlink to the bug description.
Patch level: patch level of the processor. Check this value against the rcs name value given by the -info option of the processor (you can use the esterel -info command).
Architectures: links to the new version of the processor for the known architectures.

Incorrect circuit translation

Description

The circuit translation may be incorrect in some cases, resulting in wrong code.

State

Fixed.

Back to processor table.

Wrong C Code Generator on Solaris 5.6

Description

The C boolean equation code obtained from optimized ssc code may be wrong on Solaris 5.6. This is a known bug that was corrected, but for a strange reason, the C code generator was not compiled with the right library (common p41) on Solaris 5.6.

State

Corrected. occ processor.

Back to processor table.

Wrong Simulation Of Optimized Code.

Description

After optimization of the ssc code, simulation may be wrong. It can show a non emitted signal as emitted.

Technically, the ssc format contains pragmas which are specific information for the compiler. One of these pragma (the emitted: one) tells which signal is emitted depending on an equation value. This is used for local signals, but also for output signals.

After optimization and new ssc generation, it appears that there is no good place to put the emitted: pragmas, since optimized and non optimized have same behavior, but not the same internal logic. As these pragma are used by the C simulation code, one may see wrong outputs. The behavior is respected, but the simulation output signal trace is wrong.

The work around is to suppress the emitted: pragmas in the optimized ssc code. To do this, we provide scripts. The scripts distribution contains help.

State

to be corrected, work around using scripts.

Back to processor table.

Wrong Optimized OC Code

Description

Code generation is incorrect when using the -O option for automaton code (options -A -O or -v3 and -O). Unfortunately, the generated C code compiles, which makes the bug nasty.

PLEASE DO NOT USE OPTION -O UNTIL FURTHER NOTICE

State

To be corrected.

Back to processor table.

Building A Textual Simulator On Solaris.

Description

Do not use /usr/ucb/cc to build a textual simulator with the simulation library libcsimul.a. Use instead cc from SparcWorks, or gcc. libcsimul.a internally uses setjump and the associated structures defined in the the C library used by /usr/ucb/cc differ from the standard ones.

Here is what happens with the wristwatch example:

$ cd /wristwatch
$ make -f makefile.Unix CC=/opt/SUNWspro/bin/cc
$ ./sww
WRISTWATCH> ;
--- Output: MAIN_DISPLAY(1:00:00 24H) MINI_DISPLAY(1-1) ALPHABETIC_DISPLAY("SU") CHIME_STATUS(false) STOPWATCH_RUN_STATUS(false) STOPWATCH_LAP_STATUS(false) ALARM_STATUS(false) 
WRISTWATCH> .
$ make -f makefile.Unix CC=/usr/ucb/cc
$ ./sww
WRISTWATCH> ;
--- Output: 6 "1:00:00 24H" 7 "1-1" 8 """SU""" 11 false 12 false 13 false 14 false 
WRISTWATCH> .
$

State

No fix.

Back to processor table.

Incorrect single verification for acyclic circuits with input relations.

Description

The single signal verification consists in verifying that each single is never instantaneously multiply emitted. The analysis depends on the reachable state space and the input care set defined by the user defined input relations. The single signal verification was incorrect when dealing with acyclic circuits that have relations on inputs. The input relations where omitted and not considered in the analysis in this particular case.

State

Fixed. Patch as a new binary for the causality analyzer processos sccausal available.

Back to processor table.

Last modified: Mon Apr 10 12:05:13 MET DST 2000