Presentation

 

The BASICOPT processor is specifically targeted for the optimization of large sequential circuits generated from ESTEREL specifications.

There are two possible optimization strategies, depending on the chosen target, which can be hardware circuits or software code. The options corresponding to these targets are -speed for circuits and -area for software.

• The -speed option minimizes the critical path of the circuits, which is the longest path linking a combinational input to a combinational output of the circuit.
• The -area option minimizes the number of literals in the (sum of products) description, thus minimizing the size of the generated code.

In both cases, the optimization starts by calling a SIS [4] script that performs only combinational optimization of the circuit. Then the REMLATCH processor is called to optimize the state encoding of the circuit. Finally, another call to the SIS script is used to reduce the combinational logic introduced by the sequential optimization of REMLATCH. The minimisation algorithms used by SIS and REMLATCH are based on heuristics and in some cases their interaction may generate a final result that is worse than the initial circuit.

The options to the REMLATCH processor and to the SIS script are chosen according to the general option (-speed or -area) given by the user.

Both SIS and REMLATCH can use a priori information given by the user as ``don't care'' sets to improve the result of the optimization. The -rel filename.blif option of the BASICOPT processor allows to specify such information by the relation file filename.blif. This information is then passed to the above processors. For circuits generated from the ESTEREL synchronous language the relation file is automatically generated by the compiler (see ESTEREL, SIS and REMLATCH documentations).