Task: C.1
Task Leader: SICS
Participants: SICS 10 mm, INRIA 1 mm, UTS 1 mm
From: T0 To: T0+24
Input from: A.1, A.2, C.2, C.3, D.1
Output to: A.1, C.2, C.3, D.1, D.2, D.3
Deliverable: SICS-1 (Report): A prototype of a parallel
execution environment supporting ILP
Due at: T0+24
Milestones: First draft version at T0+12.
Description:
We will use our execution environment for parallel processing
(parallel xkernel) and gradually introduce our work on integrated
layer processing. We will investigate how to partition ILP/ALF
over processors and how to increase the potential parallelism. The
work will be experimental and hence the results will be prototypes and reports
on achievable speed-ups.