Hot Interconnects VI

["Chase Bailey" <chase@cisco.com>]

*Sorry for any duplications*

********************************************************************

HOT INTERCONNECTS 6
August 13-15, 1998
Memorial Auditorium, Stanford University, Stanford, California

For registration and up to date information visit Symposium web site at
www.hoti.org

A Symposium on High Performance Interconnects, from system buses and
interfaces to networks. HOT Interconnects 6 brings together designers
and architects of high-performance chips, software, and systems.
Presentations focus on up-to-the-minutes real developments. This
symposium is a forum for engineers and researchers to highlight their
leading-edge designs. Three days of tutorials and techincal sessions
will keep you on top of the industry.
***************************************
Technical Program
Thursday, August 13

7:30 am: Registration
9:00-10:00 am: Keynote -
Challenges for Networking Companies in the 21st Century: A Business
Perspective
Charles Giancarlo, Vice President of Global Alliances at Cisco Systems

Charles Giancarlo is Vice President of Global Alliances at Cisco
Systems.  Prior to joining Cisco, Mr. Giancarlo was Vice President,
responsible for product marketing and corporate development for Kalpana,
Inc. Mr. Giancarlo is widely recognized for his contributions in the ATM
and LAN switching marketplace. Prior to Kalpana, Mr. Giancarlo served as
the Vice President of Marketing for Adaptive Corporation, which
developed the industry's first Asynchronous Transfer Mode (ATM) product
for the LAN market. During his four-year tenure at Adaptive, Mr.
Giancarlo co-founded the ATM Forum, an international consortium of more
than 350 vendors and users, where he served on the Board of Directors
for three years.

While at Adaptive, Mr. Giancarlo developed and patented many industry
firsts, including ATM LAN Emulation, Virtual LAN Technology, ATM
Ratebased Flow Control and the industry's first ATM SAR chipset. As
co-founder of O'Dowd Communications, Giancarlo designed and patented the
first cell switch used for data communications.  He also holds a patent
for the first fully digital commercial codec-filter, which he developed
when employed as a lead engineer for Siemens AG.

He holds an M.B.A. from Harvard University and a M.S. and B.S. in
Electrical Engineering from University of California, Berkeley, and
Brown University respectively.

10:00 - 10:30 am: Break

10:30 am-12:00 pm : Fast Routers and Lookups
Chair : Nick McKeown, Stanford University

Building Fast Routers - G. Varghese, Washington University
IP Address Lookup - A. Moestedt, Swedish Institute of Computer Science
Architecture of the Avici Terabit Switch - B. Dally, Stanford University

Detour: A Case for a Virtual Internet - Tom Anderson, University of
Washington

12:00 - 1:30 pm: Lunch

1:30-3:00pm : Twisted Pair and Cable
Chair : Chase Bailey, Cisco Systems

Moving Towards Friendly DSLs - J. Cioffi, Stanford University
Cable Modem Technology - Limb, Georgia Tech
What's Wrong with Cable Technology - C. Thacker, Microsoft
Simulation Study of Backbone Provisioning - J. Yee, Com21

3:00 - 3:30 pm: Break

3:30-5:00 pm : Switching
Chair : Craig Partridge, GTE (BBN)

Simultaneous Bi-directional Transceiver Logic - K. Ishibashi, Hitachi
Design and Implementation of a Fast Crossbar Scheduler - Pankaj Gupta,
Cisco Systems
Implementation of Atlas I: A Single Chip - Katevenis, FORTH
T-Cross Point Switch Architecture - Larson, UC San Diego

5:00-7:00 pm : Dinner Reception

7:00-8:30 pm : Panel - What I Love to Hate
Chair: Steve Deering, Cisco Systems

Panelists: Steve Deering, Cisco Systems; Hemant Kanakia, Torrent
Systems; Chuck Thacker, Microsoft
 ***************************************
Friday, August 14

9:00-10:00 am : Keynote -
Grand Challenges of the Internet

Van Jacobson, Group Leader for the Network Research Group,  Lawrence
Berkeley National Laboratory

10:00 - 10:30 am: Break

10:30-11:15 am : Server Interconnects
Chair : Bill Dally

Using NUMA Interconnects - S. Kleiman, Network Appliances
The NCR Worldmark Family BYNET MPP - R. McMillen, NCR

11:15 am-12:00 pm : Network Interfaces
Chair : Randy Rettberg

StarT-X; A one year exercise in Network Interface Engineering - J. Hoe,
MIT
Architecture Considerations for High Performance - S. Muller, Sun

12:00 - 1:30 pm: Lunch

1:30-3:00 pm : Potpourri
Chair : Charles Thacker

Interference Detection and Avoidance Techniques for Wireless
Infrastructure - N. Furukawa, GTE
ACTIVE Interconnects - J. Smith, University of Penn
Design Considerations for 1000BaseT - R. Paripatyadar, ControlNet

3:00 - 3:30 pm: Break

3:30-4:15 pm : Fast Links
Chair : Martin Izzard

Serial Link Backplanes - M. Laor, Cisco Systems
System Applications of Parallel Optics - L. Buckman, Hewlett Packard

***************************************
Saturday, August 15
Tutorial Sessions

8:30 am to 12:00 pm: Morning Tutorial
Voice Over IP Systems
Dave Oran, Cisco Systems

This tutorial provides a system-level understanding of Voice-over-IP
systems and provides a basic understanding of all the components
necessary to have a toll-quality telephony service using the technology.
The tutorial covers:

Audio endpoint design, including coding and voice compression basics,
echo cancellation, packetization, and more advanced techniques such as
FEC, mixing, and adaptive jitter buffer algorithms. Network design,
including voice transport protocols (RTP/RTCP), and quality of service
mechanisms (RED, WFQ, RSVP, TOS etc.) applicable to large scale voice
transport. Call control and signaling methodologies, including H.323,
SIP, SGCP in the IP world, and legacy PSTN signaling including ISDN PRI
and SS7.

David Oran is a Distinguished Engineer at Cisco System, responsible
primarily for the architecture and overall design of Cisco's VoIP
products. He also consults on a variety of other areas at Cisco,
including backbone network design, routing protocols, and quality of
service methods.

Prior to joining Cisco Mr. Oran was a Senior Consulting engineer at
Digital Equipment Corporation, where he was Technical Director for the
Mobile Software Business.

Mr Oran's main interests lie in the area of the design and
implementation of distributed algorithms for computer networks. He was a
member of the DECnet architecture group and contributed to the design of
key elements of DECnet through 3 iterations of its evolution. He was the
designer of the DNA Naming Service, a highly advanced distributed
directory system which was adopted by the Open Software Foundation as
the local directory component of its comprehensive Distributed Computing
Environment product set. Mr. Oran holds a number of patents and patents
pending for his work on distributed algorithms.

In the area of networking standards, Mr. Oran was the head of the
routing standards group in ISO and was editor for a number of important
packet-switching and routing standards, including the OSI Routing
Framework, the ESIS Protocol, and the Intra-domain ISIS Protocol. He
also is group leader for the Integrated Services over Slow Links group
of the IETF, and served on the routing and addressing group of the
Internet Activities Board, which developed technical alternatives for
enhancing the Internet protocol suite to deal with the explosive growth
of the system.

Mr. Oran was the editor the journal Computer Communication Review from
1991-95. He is the author a a number of technical articles and papers in
the areas of protocol design and distributed systems architecture. He
also serves on peer review panels for the USA National Science
Foundation program in computer networking, and on the program committees
of a number of technical conferences, including the SIGCOMM and Hot
Interconnects conferences.

Mr. Oran holds a B.A. in Physics and English from Haverford College, and
has graduate level training in Magnetospheric Geophysics.

1:30 pm to 5:00 pm Afternoon Tutorial
Design of High-Speed I/O Interfaces
Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos : Stanford
Universtity

This tutorial will examine the basic components needed to build
high-speed electrical links including driver, receiver and phase-locked
loop components. Example CMOS implementations will be presented, and
limitations of these circuits will also be discussed.

Mark Horowitz is the Yahoo Founder's Professor of Electrical Engineering
and Computer Science at Stanford University. He received his BS and MS
in Electrical Engineering from MIT in 1978, and his Ph.D. from Stanford
in 1984. Dr. Horowitz is the recipient of a 1985 Presidential Young
Investigator Award, and an IBM Faculty development award, as well as the
1993 best paper award at the International Solid State Circuits
Conference.

Dr Horowitz's research area is in digital system design, and he has lead
a number of processor designs including MIPS-X, one of the first
processors to include an on-chip instruction cache, TORCH, a
statically-scheduled, superscalar processor that supported speculative
execution, and FLASH, a flexible DSM machine. He has also worked in a
number of other chip design areas including high-speed, and low-power
memory design, high-bandwidth interfaces, and fast floating point. In
1990 he took leave from Stanford to help start Rambus Inc, a company
designing high-bandwidth memory interface technology. His current
research includes multiprocessor design, low power circuits, memory
design, and high-speed links.

Chih-Kong Ken Yang received the B.S. and M.S degrees in electrical
Engineering from Stanford University, Stanford, in 1992. He is currently
pursuing the Ph.D. degree at Stanford University. His research is in the
area of circuit design for multi-gigabit links. Mr. Yang is a member of
Tau Beta Pi and Phi Beta Kappa.

Stefanos Sidiropoulos received the B.S. and M.S. degrees in Computer
Science from the University of Crete, Greece, and the Ph.D. degree in
Electrical Engineering from Stanford, CA in 1998. He has worked on
circuit design and CAD tools at DEC, IIT, SGI He is currently with
Rambus Inc, where he is designing DRAM interface circuits. His interests
are in high-speed circuit design, and CAD tools.

***************************************
Organizing Committee
                       General Chair - Hasan S. Alkhatib, TTC of Silicon
Valley
                       Vice Chair - Diane Smith, Santa Clara University
                       Program Co-chairs -
                       Nick McKeown, Stanford University, and
                       Chase Bailey, Cisco Systems
                       Treasurer - Qiang Li, Santa Clara University
                       Publicity - Kristina Scott, Visa
                       Tutorials - Weijia Shang, Santa Clara University
                       Local Arrangements -
                       Edin Hodzic, AT&T Labs &
                       Kersten Barney, Stanford University
                       Proceedings - Vikki Wei, Auspex Systems
                       Web Master - Bruce Wootton, TTC of Silicon Valley

Program Committee
                       Bill Dally, Stanford University
                       Chuck Thacker, Microsoft
                       Craig Partridge, BBN
                       Dan Pitt, Bay Networks
                       Dave Oran, Cisco Systems
                       Greg Chesson, SGI
                       James Luciani, Bay Networks
                       Kathleen Nichols, Bay Networks
                       Mark Horowitz, Stanford University
                       Martin Izzard, Texas Instruments
                       Qiang Li, Santa Clara University
                       Randy Rettberf, Sun Microsystems
                       Steve Deering, Cisco Systems

For Registration and other information, please, visit our web site at
www.hoti.org



/chase
Chase Bailey,  Principal Technologist, Cisco Systems
408.527.3765, Fax: 408.527.9215, chase@cisco.com