Logical Time in Model-Driven Engineering
- Robert B. France, Professor Colorado State University
Suzanne Graf, Directeur de Recherche CNRS, Verimag
Jean-Pierre Talpin, Directeur de Recherche INRIA, IRISA
- François Terrier, Directeur de Recherche CEA, Professeur INSTN
- Charles André, Professeur UNS
Robert de Simone, Directeur de Recherche INRIA
Keywords: Logical Time - MARTE - Model-Driven Engineering
Abstract: CCSL has arisen from different inspiring models in an
attempt to abstract away the data and the algorithms, and to focus on events
and control. Even though CCSL was initially defined as the time model of the
UML profile for MARTE, it has now become a full-fledged domain-specific
modeling language for capturing causal, chronological and timed relationships.
It is intended to be used as a complement of other syntactic models that capture
the data structure, the architecture and the algorithm.
This work starts by describing the historical models of concurrency that have
inspired the construction of CCSL. Then, CCSL is introduced and used to build
libraries dedicated to two emerging standard models from the automotive
(East-ADL) and the avionic (AADL) domains. Finally, we discuss an
observer-based technique to verify implementations in different languages
(Esterel, VHDL) against a CCSL specification.