CCSL: specifying clock constraints with UML/MARTE
Keywords: UML profile, Time model, MARTE
Abstract:
The Object Management Group (OMG) Unified Modeling Manguage (UML) profile for
Modeling and Analysis of Real-Time and Embedded systems (MARTE) aims at using
the general-purpose modeling language UML in the domain of Real-Time and Embedded
(RTE) systems. To achieve this goal, it is absolutely required to introduce inside
the mainly untimed UML an unambiguous time structure which MARTE model elements
can rely on to build precise models amenable to formal analysis. The MARTE Time
model has defined such a structure. We have also defined a non-normative concrete
syntax called the Clock Constraint Specification Language (CCSL) to demonstrate
what can be done based on this structure.
This paper gives a brief overview of
this syntax and its formal semantics, and shows how existing UML model elements
can be used to apply this syntax in a graphical way and benefit from the semantics.
© 2008 Springer.
@article{ISSE_mallet,
author = {Fr\'ed\'eric Mallet and
Charles Andr\'e and
Robert de Simone},
title = {{CCSL}: specifying clock constraints with {UML/Marte}},
journal = {ISSE},
volume = {4},
number = {3},
year = {2008},
pages = {309--314},
ee = {http://dx.doi.org/10.1007/s11334-008-0055-2}
}