Abstract: Just as component re-use is becoming increasingly important in the design of systems-on-chip and parallel computing systems, so too is re-use of components in computer architecture simulation environments. Fundamental to both real and simulated systems is the clocking strategy. In this paper we present a behavioural design pattern to efficiently model the clock mechanism of hardware architectures. We illustrate how this pattern can increase reusability and reduce modifications when the synchronisation policy has to evolve or when components have to be included in larger architectures such as mesh networks.